Michał Jabłoński
Avionics Systems Architect · Avionics & Embedded Systems
Warsaw, Poland
Avionics Systems Architect with over a decade of experience designing IMA (Integrated Modular Avionics) platforms for commercial aircraft. Leads system-level architecture definition, AFDX network topology design, and partitioning strategy for hosted applications. Deep familiarity with DO-178C/DO-254 design assurance frameworks and EASA/FAA certification processes for avionics systems.
Expertise
- Integrated Modular Avionics (IMA) architecture
- ARINC 664 / AFDX network design
- avionics system partitioning
- DO-178C and DO-254 design assurance
- avionics certification strategy
Technologies
Work History
2025-02
MBSE (Model-Based Systems Engineering) migration for avionics architecture documentation — migrated 600+ avionics system requirements from Word documents into Capella, establishing architecture model as the single source of truth.
Challenge: Migrating requirements from unstructured Word documents to a structured Capella model required significant interpretation — many legacy requirements were ambiguous or conflated multiple constraints. The migration took twice as long as estimated because of the required clarification loop with system engineers.
Learned: Requirements quality problems that were tolerable in document form become blockers in MBSE tools. The migration revealed that ~20% of legacy requirements needed rewriting before they could be modeled — MBSE accelerates the discovery of requirements debt.
2024-04
Avionics certification strategy document for the new program — defined the means of compliance for DO-178C and DO-254 objectives, identified delegated DER activities, and established the software/hardware design assurance plan.
Challenge: The program timeline required concurrent FAA and EASA certification. FAA AC 20-115D and EASA AMC 20-115D have subtle interpretation differences that required explicit coordination with both authorities on 4 specific compliance points.
Learned: Concurrent FAA/EASA certification requires early bilateral coordination on interpretation differences. Waiting until the compliance matrix is complete to surface disagreements is too late — regulatory divergence should be identified and resolved at the PSAC/PHAC stage.
2023-09
AFDX network design for a new aircraft — defined virtual link topology, bandwidth allocation groups (BAG), and jitter bounds for 340 virtual links. Performed end-to-end latency analysis for all safety-critical data flows.
Challenge: The AFDX switch configuration tool (proprietary to the switch vendor) had a bug in the jitter calculation for multi-hop virtual links — it was underestimating worst-case jitter by 30%. Discovered the error by implementing an independent Python-based latency analysis using network calculus.
Learned: Never rely solely on vendor tools for safety-critical timing analysis. Implementing an independent calculation using published network calculus methods caught a significant error that would have resulted in an underspecified jitter budget.
2023-03
IMA platform architecture definition for an avionics retrofit program — defined the partitioning model for 12 applications hosted on 3 GPM (General Processing Modules), covering FCS, FMS, and display systems.
Challenge: One hosted application required DAL A partitioning while sharing a GPM with DAL C applications. ARINC 653 spatial and temporal partitioning was required but the target RTOS (VxWorks 653) had an undocumented latency jitter on partition context switches that exceeded the DAL A timing budget.
Learned: IMA partitioning for mixed-DAL configurations must include a RTOS timing characterization test before architecture is baselined. Undocumented jitter in partition scheduling is a common source of late-program integration problems.