Norbert Makowski
Embedded Software Engineer · Avionics & Embedded Systems
Warsaw, Poland
Embedded Software Engineer specializing in VxWorks RTOS board support package (BSP) development and device driver implementation for avionics hardware. Responsible for the lowest layers of the avionics software stack — hardware abstraction, interrupt service routines, memory-mapped I/O, and real-time task scheduling. Develops under DO-178C Level C/D assurance.
Expertise
- VxWorks RTOS BSP development
- device driver development (C)
- real-time scheduling and priority management
- embedded memory management
- DO-178C Level C/D embedded software
Technologies
Work History
2025-01
Memory partitioning implementation for ARINC 653 spatial isolation — configured VxWorks 653 memory protection units (MPU) to enforce spatial partitioning between avionics applications hosted on the same GPM.
Challenge: MPU region count on the processor was limited to 16 regions while the partitioning specification required 23 regions to fully isolate all hosted applications. Required a creative solution: combining memory regions where applications had identical access rights and using guard regions only at partition boundaries.
Learned: Hardware MPU region limitations must be verified against the partitioning requirements during architecture definition, not during implementation. Running out of MPU regions mid-implementation forces compromises in the partitioning scheme that require DER justification.
2024-04
DMA (Direct Memory Access) driver for high-bandwidth ARINC 664 network interface card — implemented scatter-gather DMA transfers for zero-copy packet reception and transmission in VxWorks 7.
Challenge: Scatter-gather DMA with zero-copy required careful alignment of DMA descriptors and data buffers to cache line boundaries. Misaligned buffers caused sporadic cache coherency failures — silent data corruption that was not caught by checksums because the DMA engine bypassed the cache.
Learned: DMA driver development requires explicit cache management — VxWorks does not automatically handle cache coherency for DMA operations. Any buffer shared between DMA and CPU must be cache-aligned and cache-flushed/invalidated explicitly at DMA descriptor boundaries.
2023-09
Priority inversion debugging for real-time task scheduler — identified and resolved a priority inversion scenario where a low-priority display update task was blocking a high-priority navigation data task.
Challenge: Priority inversion was intermittent and only occurred under high system load — extremely difficult to reproduce in test. Used VxWorks WindView real-time trace tool to capture task scheduling events and identify the blocking sequence. The fix required adding a priority inheritance mutex for the shared data buffer.
Learned: Priority inversion in RTOS applications is notoriously hard to detect in testing because it only occurs under specific load conditions. VxWorks WindView task trace is an essential diagnostic tool — instrument the system from the start, not after problems are observed.
2023-03
BSP development for a new processor board (PowerPC e6500 dual-core) — implemented VxWorks 7 BSP including clock drivers, UART/I2C/SPI peripheral drivers, and memory controller initialization.
Challenge: The L2 cache controller required an initialization sequence that differed from the BSP template for previous PowerPC variants — the cache locking register must be written before enabling the L2, but the VxWorks BSP template inverted this order. Caused intermittent cache coherency failures that only manifested under load.
Learned: BSP bring-up requires reading the processor hardware reference manual, not just adapting the existing BSP template. Initialization sequence requirements often differ between processor generations in ways that are not reflected in any template.