Przemysław Ostrowski
Avionics Hardware Engineer — DO-254 · Avionics & Embedded Systems
Warsaw, Poland
Avionics Hardware Engineer specializing in FPGA-based signal processing for avionics applications under DO-254 DAL C assurance. Designs and verifies VHDL IP cores for ADC/DAC interfaces, discrete I/O, and ARINC 429 communication. Experienced in executing the full DO-254 lifecycle from hardware requirements capture through final verification and DER coordination.
Expertise
- FPGA design for avionics (Xilinx Zynq)
- DO-254 DAL C hardware design assurance
- analog signal conditioning (ADC/DAC)
- VHDL design and simulation
- hardware design review and verification
Technologies
Work History
2025-01
FPGA configuration security hardening — implemented bitstream encryption using Xilinx eFUSE AES-256 to prevent readback of proprietary IP from deployed FPGA boards. Documented the key management procedure.
Challenge: AES key programming via eFUSE is irreversible — once programmed, the device can only load encrypted bitstreams. A test batch of 5 boards was programmed with the wrong key due to a configuration file error, making them permanently unusable. Implemented a mandatory two-person verification step before any eFUSE programming.
Learned: Irreversible hardware programming operations require mandatory dual-person authorization checks. A two-person sign-off on the key file before eFUSE programming is a minimal safeguard — the cost of verification is trivial compared to the cost of a wrong key.
2024-05
ARINC 429 transmitter/receiver FPGA IP core — implemented full ARINC 429 bitstream decoder and encoder in VHDL, including label filtering, parity checking, and SDI validation. Verified against ARINC 429-17 specification.
Challenge: ARINC 429 bit-rate tolerance is ±1% — at 100kbps, the receiver must correctly decode words with bit periods ranging from 9.9µs to 10.1µs. The FPGA clock (40 MHz) gave a 25ns resolution, which was marginal for the timing tolerance at temperature extremes. Required oversampling at 8x and majority voting.
Learned: ARINC 429 receiver oversampling requirements must be analyzed against the FPGA clock frequency during architecture definition. A too-slow FPGA clock leaves insufficient timing resolution for robust decoding at specification limits.
2023-11
DO-254 Hardware Design Assurance Level C compliance activities — authored PHAC (Plan for Hardware Aspects of Certification), HAS (Hardware Accomplishment Summary), and hardware requirements document. Coordinated 3 DER review sessions.
Challenge: DO-254 requires that 100% of hardware requirements are traceable to verification test procedures. A gap analysis revealed 23 requirements with no corresponding verification procedure — these were requirements captured late in the design phase after the verification plan was written.
Learned: Requirements traceability to verification must be maintained throughout the design — not audited at the end. Adding a CI check that flags untraced requirements after every DOORS baseline prevents traceability debt from accumulating.
2023-04
FPGA signal conditioning design for a new sensor interface card — implemented VHDL ADC interface for 16 analog sensor channels with digital filtering, offset correction, and range validation. DO-254 DAL C.
Challenge: The ADC SPI interface had a timing violation at 40 MHz clock — setup time margin was negative (-2ns) at worst-case temperature corner. Required a pipeline stage insertion in the SPI capture logic, but this changed the timing of downstream processing stages that had already been verified.
Learned: Timing closure issues in FPGA designs require re-running the full verification suite after any netlist change — even a single pipeline stage insertion can introduce new functional issues in adjacent logic. Never re-run only the affected module tests.